bug or wrong way?

hi all,

I use a TSE IP core in my project, but have a problem with simulation.

In 'Settings -> EDA Tool Settings -> Simulation', I set 'Tool name' as 'ModelSim' and give the path of ModelSim in 'Options -> General -> EDA Tool Options'. The testbench is also correctly set. After Analysis & Synthesis ( I've tried complete compile but no use), click the 'Tools -> Run Simulation Tool -> RTL Simulation'. Modelsim program opens and compiles the library. THen the problem comes. It runs for a while(long enough) and stops, but gives no signal in the TSE output pins. All the pins show 'U'. The result gives me the impression that the TSE module is not correctly linked to the testbench.

As we know, the Quartus or ModelSim will generate a .do file in the directory 'simulation\modelsim', and run a 'do TSE_tester_run_msim_rtl_vhdl.do' command when simulation. The problem is just here. I change the order of 'tse_mac_small.vho' and 'tse_mac_small.vhd', then run 'do TSE_tester_run_msim_rtl_vhdl.do', and the simulation gives the right result!

my question is that, is the wrong order a bug or I have used modelsim in the wrong way? what's the difference between .vho and .vhd?

my demo project 'TSE_tester' is attatched below.

Thanks in advance.