Bug fix for Quartus 13 .0 or 13.0 sp1 that fixes OR gates acting like AND gates and AND gates acting like OR gates

Sure. It's a real simple entity. Though I think I discovered how to do a work around, even though I don't understand why it works

If I NOT both button inputs before ORing them, then it works.. Otherwise it works like an AND gate

The pins that the buttons connect too have weak pull up resistors on them configured in the pin planner. Pin reads input when button is pressed grounding the pin. Cyclone II FPGA

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity invertor is

Port ( PB: in STD_LOGIC_vector(1 downto 0);

LED : out STD_LOGIC);

end invertor;

architecture Behavioral of invertor is

signal led_out:STD_LOGIC :='0';

begin

process (PB)

begin

--LED <= PB(0) or PB(1); this works like an AND gate. LED is lite until both buttons pressed. I ave no idea why. Works fine on a different board

-- LED <= not PB(0) or (not PB(1))); WOrks like an OR gate. LED goes off if either button is pressed

LED <=not( not PB(0) or (not PB(1))); -- This also works, Just the opposite of above. LED is off until either button is pressed

end process;

end Behavioral;