Honored Contributor
Honored ContributorI can generate for Synthesis only... but when I try to generate simulation and the testbench I get this ... is there a trick or do I need to provide some BFM or monitor ?
(the errors below are not very helpful ). The goal here is to have QSYS generate the synthesis and testbench so I can do the right thing and run some simulation first. Error: monitor_1_0: monitor_1 does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis. Error: Generation stopped, 7 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 2 Warnings Error: monitor_1_0: monitor_1 does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis. Error: Generation stopped, 7 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 4 Warnings Error: There were errors creating the testbench system.
