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Altera_Forum's avatar
Altera_Forum
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11 years ago

Avalon MM "sniffer" connections in QSYS

I seem to be stuck in connecting a new QSYS component into my system that I have generated. The new component, lets call it bus_tracker, monitors the data output of an Avalon MM master for ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It should be that easy!

In the MMM_hw.tcl file the line: set_interface_property slave bridgestomaster 1 does the trick. And if effectively maps the addresses just like Altera's pipelinedBridge does. I made a small Qsys project to see how it all went down :)

Why would you go back to Verilog? To simulate it all? I am currently transitioning to myhdl (http://www.myhdl.org/) - simulating with the power of Python, and get VHDL-code (or Verilog for that matter) to plug into Qsys