Avalon MM "sniffer" connections in QSYS

Thanks for the nexample Josy,

I have captured it and will have a go at implementing your example in Verilog. I worked VHDL for the past 10 + years and before that Verilog..... now I ma back to Verilog.... phew !!

It looks too easy , but I see you have a MM slave connecting across to a MM master and that exposes the MM slave signals I am interested in.

Somewhere back there or on another thread, there was mention of setting the "Bridge" attribute. I figure this tells the QSYS that somehow the bridge component takes all transactions ... I guess the memory map on the other side of the "bridge" can't conflict

with the memory map on the primary side of the bridge . ?