Avalon MM "sniffer" connections in QSYS

A few more ideas;

1. Create an Avalon-MM master that is not instantiated in the Qsys system. What this does is create a _hw.tcl file that you can use in Qsys, which results in master ports appearing in the top-level design. I had to do this to instantiate an Avalon-MM master that had VHDL entity port types that were not supported by Qsys (VHDL records).

Given that the master port is then outside of Qsys, you can do whatever you like with it, eg., instantiate whatever master you originally had, along with your probe logic.

2. Have you considered just using SignalTap II to look at the transactions you want to see?

3. Verilog allows you to probe signals within a hierarchy, so that means you could determine the name within the Qsys system, and then probe it directly ... this works in Modelsim, but I'm not sure about synthesis.

4. Use Modelsim to do your performance analysis (since you have more flexibility to probe signals).

Cheers,

Dave