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Altera_Forum's avatar
Altera_Forum
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12 years ago

Assigning pins from schematic editor and VHDL in the same project

Hi,

A basic Quartus II question please ....

I am just getting started with Quartus II, up untiil now, I have been using the schematc editor to create designs, then using the Pin assignment editor to put the I/O where I want it on the board.

I want to add a VHDL file to the project and also manually assign the I/O.

I have schematic file (.bdf) and a VHDL file (.vhd), these are currently at the same level in the Files hierarchy. I have tried assigning the pin as shown

entity rom is port (

A15 : in std_logic ;

A14 : in std_logic ;

A13 : in std_logic ;

romcs: out std_logic ) ;

end rom ;

architecture select of rom is

attribute chip_pin : string;

attribute chip_pin of A15 : signal is "G72";

begin

romcs <= A13 and A14 and A15 ;

end select ;

The first question is that I am not sure of the actual pin name. The help file says "To find the name for each pin you want to assign to a port, consult the pin table for the design's target device." The device is an EPM7128S in a PLCC package, the datasheet does not give names (as far as I can see) for the pins, so I have tried just the pin number and also with it prefixed by the LAB.

When I look in the pin-planner, the pin is still unassigned, so I am obviously doing something wrong.

Can someone give me a couple of pointers please?

Assuming that the code is correct (a big assumption) should I be able to see the pin assignment on the pin planner?

regards

Dave

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I would always do the pin assignments in the assignments editor. As your design gets larger, having assignments spread out over several files gets rather messy. Having them in the assignments editor also keeps them all in the same place.

    As to your problem... Which file is your to level? You cannot have 2 files at the same level of they are both at the top so if the schematics are the to level, is your vhdl being used? And are the vhdl pins routed through to the top level?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    thanks a lot for the reply, I will go and look into the assignments editor.

    You have picked up a fundamental error that I thought I might be making, which is why I mentioned it in the post. When the design was started, the schematic was at the top level. As I added a couple of LPMs, they appeared at the same level as the schematic, with their VHDL nested at a level below. When I added my simple VHDL I added it at the same level as the schematic & LPM instances.

    There is no routing of pins from the VHDL - I don't know how :-)

    I guess that should put my VHDL below the schematic in the files tree then?

    regards

    Dave