Are QII7.1 Symbol files mandatory ?

Wow,

It is not my intent to make you upset or mad.

I have been designing since the 70's, starting out on punch cards, etc.

Worked my with the best of them through the schematic days, andfor the longest time I was a schematic's rule person.

Kicking and screaming, I worked my way through PALASM, ABEL, CUPL, AHDL, VHDL and Verilog.

In the end, not having to resolve all the issue that come up over and over again with various symbol based compilers that just don't seem to ever get the into's and out-of's correct, let alone the inout-of's, I have found that just writing some simple Verilog code with all the Inout's only at the top level gets t he job done!

You asked for some help that would earn my everlasting adoration, and I offered it.

These tools are supposed to make our life easier.

That's my advise.

Sorry it rubbed you the wrong way.