Adjustable frequency generator

People do division in FPGA's all the time. You just need to normalize it. Say you need to multiply by 1.3. Normalize it to use a power of 2 division by say 1024 * 1.3 = 1331. So to multiply 12 * 1.3 you do 12 * 1331 = 15972 and then right shift by 10 (ie 2^10 = 1024) to get 15. You can round to nearest integer by adding in the highest order bit that is shifted out. For example, 15972 is 11_1110_0110_0100 binary and bit 9 is a 1 so the result is 16. So now you just need a multiplier, 1 bit adder and slice out the result.

You don't say how you want to vary the frequency. Your original post makes it seem like you are trying to steadily decrease it with each half wave and won't work as written for the reason FvM said. You could do that by decrimenting the tuneword.

For your second attempt, 20000 is not a power of 2. What do you think is going to happen when divider and counter get to 20000 and you add 1?