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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Added a few constraints to .sdc file and the whole design broke?

Hello, I am using the Arria 10 Dev. Board to test out the transceivers. I have a simple design using the Arria 10 Transciever Native PHY with enhanced PCS as well as the associated reset core and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

ref clk 644 MHz is fine - we are using exactly that as refclk for PLLs and CDR refclk in our 10GBASE-R design using Arria 10 Transceivers.

What is weird, however, is that your design works without .sdc - luck, I guess :)