Added a few constraints to .sdc file and the whole design broke?

you have defined two clocks 644MHz & 275MHz yet you haven't defined the fpga core clock of 250MHz, I assume it is PLL output, that is ok

I think the ref clk of 644MHz is way too fast and you better go as low as possible.

You may not need set clk groups as you only have one core clk and I assume quartus takes care of PHY interfacing with core logic (check if any sdc file is generated for this purpose), if so, you can safely say clk 250 domain is asynchronous, else you should cross clocks safely