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Can you explain your clocking scheme.
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Sure; the PHY is running at 14.025GHz and I have two clocks going to the FPGA. One clock, at 644MHz (I'm rounding off here for simplicity) goes to the Arria 10 Transceiver ATX PLL and is used to generate (most of) the clocks used by the PHY. The same clock goes to an IO PLL and is used to create a 250MHz clock which drives internal logic. The second clock is a 275MHz clock coming to the FPGA that is used for the CDR of the PHY. So, all the user-created logic is run off of the 250MHz clock--everything else is for the PHY and chosen from the list of possible choices.
Honored Contributor
