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Hi, pletz. Thank you for your answer.
But isn't it the path that connects the Q-port of one register to the D-port of another that the tool will check? But here, the "from nodes" and the "to nodes" are the same one, even if the tool will check the same register for hold time requirement, why the "from nodes" and the "to nodes" are both the Q-port of the register? I am just wondering if it has any meaning for this kind of timing check.
I don't know if I am right. Please point me a way. Thank you so much.
And I just encountered another setup violation report, it is much like this:
slack from nodes to nodes from clock to clock
-1.091ns COUNT[1] AVE[9] VCLK VCLK
-1.056ns COUNT[1] AVE[9] VCLK VCLK
-1.003ns COUNT[1] AVE[9] VCLK VCLK
-0.899ns COUNT[1] AVE[9] VCLK VCLK
-0.734ns COUNT[1] AVE[9] VCLK VCLK
As you see, TimeQuest found the setup violation, it is between COUNT[1] and AVE[9]. But I do not know why there are 5 reports listed! Always, there is only one listed.
Best regards.
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Hi,
if you have an clocked register Quartus has to check whether the setup and hold time requirements of the register are fullfilled.The input data needs to be stable a certain time before (setup time) and it must be stable a certain time after (hold time) the active clock edge. Your first violation is a hold time violation. That means your data coming out of the register ( it takes a certain time to propagate the signal to the out of the register, it's call tco) through the multiplexer logic is too fast. The data is not long enough stable.
You got 5 paths listed, because the timing analyzer found 5 different paths from node count[1] to node AVE[9].
Kind regards
GPK
Honored Contributor
