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Hi,
when your mux selects the HSYNC as output you have a direct feedback from register output to the input of the register. When the hold time requirement of the register is larger than the data delay, you will see such timing violation.
Kind regards
GPK
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Hi, pletz. Thank you for your answer.
But isn't it the path that connects the Q-port of one register to the D-port of another that the tool will check? But here, the "from nodes" and the "to nodes" are the same one, even if the tool will check the same register for hold time requirement, why the "from nodes" and the "to nodes" are both the Q-port of the register? I am just wondering if it has any meaning for this kind of timing check.
I don't know if I am right. Please point me a way. Thank you so much.
And I just encountered another setup violation report, it is much like this:
slack from nodes to nodes from clock to clock
-1.091ns COUNT[1] AVE[9] VCLK VCLK
-1.056ns COUNT[1] AVE[9] VCLK VCLK
-1.003ns COUNT[1] AVE[9] VCLK VCLK
-0.899ns COUNT[1] AVE[9] VCLK VCLK
-0.734ns COUNT[1] AVE[9] VCLK VCLK
As you see, TimeQuest found the setup violation, it is between COUNT[1] and AVE[9]. But I do not know why there are 5 reports listed! Always, there is only one listed.
Best regards.
Honored Contributor
