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Hi, I met with a very strange problem when using TimeQuest Timing Analyzer trying to achieve the requirement.
The analyzer reported a hold violation, but the two nodes of the violated path is exactly the same one!!! But it reported that there is a path between them and the delay is less than the required delay!
the code:
assign HSYNC_D = SEL ? 1'B1 : HSYNC;
always @(posedge VCLK or negedge Rst_n)
begin
if(!Rst_n)
HSYNC <= 1'B0;
else
HSYNC <= HSYNC_D;
end
the reported message:
slack from to from clock to clock
-0.003ns HSYNC HSYNC VCLK VCLK
so please let me know how can it happen? I am crazy about it now!
I thought it only check paths between different nodes!
Please get me out of this mess! I am waiting here. Thank you.
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Hi,
when your mux selects the HSYNC as output you have a direct feedback from register output to the input of the register. When the hold time requirement of the register is larger than the data delay, you will see such timing violation.
Kind regards
GPK
Honored Contributor
