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Altera_Forum's avatar
Altera_Forum
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10 years ago

A question about parameterized structure between interface and module

Hello everyone! I have a design that is using client/server architecture, one server module polling multiple client module periodically to check if the client module needs update, and if the clien...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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The only option here is to separate the ports as you suggest, as Verilog does now allow what you suggest.

In VHDL 2008, you can do this as you can define records with unconstrained data structures that are constrained when they are used, and this is supported in quartus.

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Hi, Mr.Tricky.

Thanks for your suggestion. The VHDL is quite a different language to verilog, and seems even more strange. I must take some more time to learn it.

Even though, you gave me another choice for my question, thanks again!