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Altera_Forum
Honored Contributor
18 years agoI just use assign "sum = a+b+c" in Verilog.
You need to be a little careful with the grouping in adder trees, matching up the bitwidths, etc. There is some discussion in this manual - www.altera.com/literature/manual/stx_cookbook.pdf www.altera.com/literature/manual/cookbook.zip