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I am running Modesim PE 6.1e but I'm not sure if it supports mixed-language. I have a feeling that it doesn't if my memory serves me correctly.
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Ok, that makes it difficult to test your VHDL with Altera's SystemVerilog verification IP.
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I am posititive of 2 things :-P
1. My simulated master (which is a couple VHDL procedures to support RD/WR is not representative of the actual hardware.
2. The actual hardware does not work the way the Altera documentation is describing it.
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Exactly. This is why you need to use a BFM from Altera (assuming of course they can write to their own specification!)
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I would like to simulate with the processor as part of the simulation but I have to figure out how to do that and I'm really in a bind time-wise. So for now I went to fixed wait states that equate to the slowest PCB in order to get
something to the software team that works. After that I can have more time to look into simulating. I got it almost completely working with fixed but the issue now is that when the processor is executing the ldbio and stbio assembly instructions to my 8-bit Avalon Slave - it is actually performing 4 reads of 8-bits...which doesn't surprise me at the same time I'm thinking what if I had to have the processor capable of reading a single byte and no others (maybe other addresses are registers that have status that clears upon a read or something)? The write indeed performs a single access but the read (a single ldbio assy instruction) performs 4 byte access.
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The mapping of instructions to bus activity is where using the simulation would be useful. This type of observation also indicates the types of tests you should include in a BFM simulation of your slave interface. That way you can add testcases that reflect actual use of the interface.
If you want to restrict your bus accesses to very specific operations, eg., all accesses are 32-bit reads/writes, then you would need to write a device driver that implemented that restriction.
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Could you point me to some documentation to get me simulating running the processor as part of the sim? Furthermore, how to I get it running my C-code in the simulation?
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I do not use the NIOS processor, so have not had to simulate it. There is an application note from Altera on the subject:
http://www.altera.com/literature/an/an351.pdf However, what you really want to begin with is a testbench that verifies your slave adheres to the Avalon specification, via the use of the Verification IP, and then once you are convinced it does, then simulate with the NIOS II processor. The caveat here will be, what if the NIOS processor is also only available in Verilog format ...
Cheers,
Dave
Honored Contributor
