waitrequest signal for Avalon MM Slave

Dave,

I am running Modesim PE 6.1e but I'm not sure if it supports mixed-language. I have a feeling that it doesn't if my memory serves me correctly.

I am posititive of 2 things :-P

1. My simulated master (which is a couple VHDL procedures to support RD/WR is not representative of the actual hardware.

2. The actual hardware does not work the way the Altera documentation is describing it.

I would like to simulate with the processor as part of the simulation but I have to figure out how to do that and I'm really in a bind time-wise. So for now I went to fixed wait states that equate to the slowest PCB in order to get something to the software team that works. After that I can have more time to look into simulating. I got it almost completely working with fixed but the issue now is that when the processor is executing the ldbio and stbio assembly instructions to my 8-bit Avalon Slave - it is actually performing 4 reads of 8-bits...which doesn't surprise me at the same time I'm thinking what if I had to have the processor capable of reading a single byte and no others (maybe other addresses are registers that have status that clears upon a read or something)? The write indeed performs a single access but the read (a single ldbio assy instruction) performs 4 byte access.

Could you point me to some documentation to get me simulating running the processor as part of the sim? Furthermore, how to I get it running my C-code in the simulation?

Thanks a lot for all your time and help