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The Slave is written in VHDL.
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Do you have a full-edition of Modelsim, i.e., can you run mixed-language simulations?
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The master is the Nios processor and the Nios is accessed via either running C code:
my_reg = IORD_8DIRECT (MYCUSTOM_MM_INTERFACE_BASE, 0x800);
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Does your simulation perform this same action using a NIOS processor?
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I'm not familiar with the other method of using a JTAG-to-Avalon-MM master for debugging - does this mean no CPU at all?
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Its another master. I use it without a CPU, but in your case, you could add it to the SOPC system and use it in addition to the CPU.
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I think of the trace signals as being the "real thing" and the simulation as being...just that...a simulation.
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In the case that you simulate exactly what you implement in hardware, the two will match.
Its not clear from our discussion that your simulation and hardware are identical. So lets establish that first.
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While I'm not saying by any means the sim is not useful - my sim works fine and yet the target has this strange behavior. In my simulation of the master I deassert chip select on the rising clock edge after waitrequest is deasserted - and that just plain works.
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But why in your simulation do you have your own master. Why not simulate with the NIOS processor in the design?
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why would the CPU stall forever if waitrequest goes low, as it does?
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I agree, its a strange problem, and the first thing I would do would be to put the same design into the simulator and try and understand if there is a difference between simulation and 'real' hardware.
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I did try inserting the BFM (never used it before and I don't know Verilog or system Verilog) but I was finding the documentation on how to make use of it - very poor.
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Yes, I agree, the documentation is not very good. Especially for simulation of VHDL designs, its downright painful ... That is why I am offering to give you an example. But you need to let me know if you can implement mixed-mode language simulation ...
Just to be clear; I'm not telling you that what you are trying to do is wrong, I'm just trying commenting on how I would attack this problem. My recommendation - simulate exactly what is in the hardware, including the NIOS II processor, or use an independently created BFM master, that way you don't have your own incorrect assumptions (or incorrect Altera documentation) folded into both your master and your slave.
Cheers,
Dave
Honored Contributor
