Honored Contributor
Honored ContributorDave,
The Slave is written in VHDL. --- Quote Start --- What is the master in this example? A NIOS processor? Have you tried other masters, eg. I use the JTAG-to-Avalon-MM master for debugging. --- Quote End --- The master is the Nios processor and the Nios is accessed via either running C code: my_reg = IORD_8DIRECT (MYCUSTOM_MM_INTERFACE_BASE, 0x800); I'm not familiar with the other method of using a JTAG-to-Avalon-MM master for debugging - does this mean no CPU at all? --- Quote Start --- Sorry, I can't really tell anything from traces. Have you created a Modelsim testbench for the design? If you don't know how to, send me the code, and I can try to create one for you. --- Quote End --- I think of the trace signals as being the "real thing" and the simulation as being...just that...a simulation. While I'm not saying by any means the sim is not useful - my sim works fine and yet the target has this strange behavior. In my simulation of the master I deassert chip select on the rising clock edge after waitrequest is deasserted - and that just plain works. Yes I have a test bech for the design, I have many of them for this whole FPGA. The trace shows the "real" waitrequest signal and the "real" chipselect signal and if we forget everything else and not even connect the address/data ports - why would the CPU stall forever if waitrequest goes low, as it does? Is there ANY situation where the Master will hold chip select asserted after my slave has deasserted waitrequest? It really seems like a bug or something to me becuase it's trivial. I even tried stretching the waitrequest signal (low time) by 2 more clocks. If the "max pending read transactions is set to 0 and I use waitrequest and no readdatavalid - shouldn't the master always release chipselect on the next clock edge after the Slave deasserts waitrequest? --- Quote Start --- The handshake depends on how you have told the system the slave responds, and that is some of the 'magic' hidden in the _hw.tcl file. Have you checked the settings in there? --- Quote End --- --- Quote Start --- --- Quote End --- There's not much magic as far as I can see - it simply has all the settings that I see in the GUI Component editor. --- Quote Start --- I think the only way you will resolve this is if you can simulate the system. I'm pretty sure you will get the same lock-up there, but you might get some useful warning messages from the Altera IP. --- Quote End --- --- Quote Start --- --- Quote End --- I have a simulation and it works fine becuase my representation of the master in behavioral simulation works just as the avalon bus spec says it should...but that is, and must be, different than the actual - which is where I'd be lost without SignalTap. I did try inserting the BFM (never used it before and I don't know Verilog or system Verilog) but I was finding the documentation on how to make use of it - very poor. The documentation talks about re-compiling an example design, rather than how to make a testbench for the BFM from scratch. I admittedly have no clue what I'm doing with the BFM and reading the doc didn't help much other than how to instantiate it in SOPC builder.
