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I do have a full behavioral simulation that works but I obviously must not be representing the Master correctly. I do need to use the proper BFM but I still don't understand a couple things:
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What language? VHDL or Verilog?
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1. How many clocks does my slave have to assert waitrequest after chip select is asserted? I believe in looking at Figure 3-3 it is implying 0 (asynchronous) but if it can be synchronous I can edge detect the chip select signal and always assert waitrequest based on that edge detect - and then clear waitrequest when my Slave is done and ready for another transfer. However, if I edge detect chipselect and set waitrequest
synchronously the processor needs at LEAST a second clock cycle to detect my slave's waitrequest.
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Figure 3-3 shows a combinatorial version of waitrequest, not an asynchronous. As I commented in the earlier post - this is a bad idea. There is no need for it. The same figure could have been drawn with waitrequest high until the slave was ready.
My general rule is; if its a slow device, eg. SRAM, then waitrequest starts out high, and deasserts after the FSM detects being selected, whereas from something like on-chip SRAM or registers, the waitrequest is there so that it can assert high during reset, but it is otherwise low. I always design synchronous interfaces to the Avalon bus, and I never use any of the tri-state components. This allows the components to be self-contained, i.e., none of the 'magic' of the component is implemented in the fabric.
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2. How many clocks does waitrequest have to be deasserted to complete the transfer?
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Each deassertion of waitrequest indicates acceptance of a transaction.
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For instance if I have asserted waitrequest for 100 clocks, and then deassert it for one clock - will the processor deassert chipselect the next cycle? (Figure 3-3 shows this but in Signal Tap this is what never happened)...???
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It should. But if you run this component in Modelsim with the verification suite, you will get warnings about the device timing out. So ultimately it depends on how your master will deal with a slow target. Generally you'd want to change the interface to a control/status and data register, i.e., write to the control register, then poll status until done (or use an interrupt), and then read the data register.
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I was trying to make my waitrequest signal look exactly as it does in Figure 3-3, which is impossible without an asynchronous preset. And even when I made the signal look just as it does in Figure 3-3 (verified in Signal Tap) - it would hang the CPU once I tried to access that Slave.
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The Avalon bus has a lot of implementation options. Although Figure 3-3 represents a valid implementation, its a bad one.
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do you have any example code for the actual synthesizable slave using waitrequest?
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Yes, I have several in VHDL.
However, unless you have the full edition of Modelsim, you cannot simulate with the Avalon-MM BFM and bus monitors, etc.
What type of example would you like to see? A device with a fixed latency, eg. a character LCD controller or SRAM? A device with a variable latency?
Cheers,
Dave
Honored Contributor
