waitrequest signal for Avalon MM Slave

Dave,

Thanks very much for the prompt and detailed response.

I do have a full behavioral simulation that works but I obviously must not be representing the Master correctly. I do need to use the proper BFM but I still don't understand a couple things:

1. How many clocks does my slave have to assert waitrequest after chip select is asserted? I believe in looking at Figure 3-3 it is implying 0 (asynchronous) but if it can be synchronous I can edge detect the chip select signal and always assert waitrequest based on that edge detect - and then clear waitrequest when my Slave is done and ready for another transfer. However, if I edge detect chipselect and set waitrequest synchronously the processor needs at LEAST a second clock cycle to detect my slave's waitrequest.

2. How many clocks does waitrequest have to be deasserted to complete the transfer? For instance if I have asserted waitrequest for 100 clocks, and then deassert it for one clock - will the processor deassert chipselect the next cycle? (Figure 3-3 shows this but in Signal Tap this is what never happened)...???

I was trying to make my waitrequest signal look exactly as it does in Figure 3-3, which is impossible without an asynchronous preset. And even when I made the signal look just as it does in Figure 3-3 (verified in Signal Tap) - it would hang the CPU once I tried to access that Slave.

do you have any example code for the actual synthesizable slave using waitrequest?

John