Honored Contributor
Honored ContributorHi,
--- Quote Start --- This read will be unconditional, the only question is the actual condition(s) for a 'D' phase stall (ie a re-execute for the same opcode word). --- Quote End --- Of course, the 'D' phase stall is evoked in the case of 'Data Hazard'. --- Quote Start --- AFAIK, an instruction can use registers that are modified by the previous one (at least for calculations, maybe when used as an address in a load or store instruction this might cause a hazard and thus stall the pipeline). -Michael --- Quote End --- And of course, Nios2/f core has the 'forwarding mechanism'. May be, those paths are from the output of 'Execute', 'Align', and 'Write Back' stage, and I think (may be) the 'Memory' stage doesn't have one for the sake of simplicity, because the load instruction needs at least 2 clocks when the core uses the data cache and only the 'Align' stage can make stall after 'Execution' stage (this means that the 'Memory' stage is a dummy stage for simple instructions, for example, add or sub). May be the Nios2/f has 'Score Board' algorithm and the latest value is supplied from forwarding paths when the target operand is existing in these stage, so I think the 'D' phase stall is evoked when the next instruction needs the result of memory read or the result of 'Memory' stage. Kazu
