Honored Contributor
Honored ContributorHi,
Did you hack Nios2 core?:D --- Quote Start --- I meant to say that the 'ra' and 'rb' bits (readra and readrb) are ignored. Think of what happens during the 'Decode' pipeline phase: - opcode bits 31-27 read register file (M9K) port 'a'. - opcode bits 26-22 read register file port 'b' (dual ported reads) - D phase stall is detected (write pending to either register [1]). Now we have three 32bit values which are fed into all the ALU functions during the 'Execute' pipeline phase (including the combinatorial custom instructions), all will generate their result based on the 96 input bits. The opcode bits 5-0 (opcode) and bits 13-6 (custom code) act as a big 'mux on the result of all the instruction logic and a 'write-back' flag (bit 14 for custom) these are latched for writing to the register file next clock [2]. --- Quote End --- The Nios2/f CPU pipeline is composed of 6 stages like Fetch -- Decode -- Execute -- Memory -- Align -- Write Back. Each instruction must get operands before it enters the 'Execute' stage. But the register files are made from 'Embedded Memories', so I think that the register files are always read from the 'Fetch' stage even for the instructions which do NOT need operand values, because the Embedded Memory needs 1 clock for its read (and write) access. Kazu
