Usage of pipeline bridge and clock crossing bridge

You don't always need bridges. SOPC Builder and QSys can connect Avalon Memory mapped masters and slaves that use different clocks and will add some clock domain crossing logic f needed, so you could just make your system without any bridges. Such a solution is rather slow though, as it can't pipeline several requests between the two clock domains. So such a solution is fine if the master only does single access from time to time (a PIO register, for example) but if you need a higher throughput, then you should add a clock crossing bridge.

For the pipeline bridges, you can start first without them and check if you pass the timing requirements. Their main purpose is to add a pipeline stage and can be useful when lots of components are connected together (lots of slaves on one master, lots of masters on one slave, or any combination of the above). I usually find it simpler to first compile a design without pipeline bridges, and then check with Timequest where the failing paths are and add pipeline bridges only on those paths, until I meet the timing requirements.