Honored Contributor
Honored ContributorThanks a lot!
Can you tell me if these defines are the ones I'm interested in (p. 10 in AN 440)?: # define BB_ALLOC(size) ncpalloc(size) # define BB_FREE(ptr) ncpfree(ptr) # define LB_ALLOC(size) ncpalloc(size) # define LB_FREE(ptr) ncpfree(ptr) On this page it is also mentioned that this RAM should be placed in an uncached region under certain circumstances but I haven't really understood that part. Does the driver handle this for me? I've read in cache and tightly-coupled memorycache and tightly-coupled memory (http://www.altera.com/literature/hb/nios2/n2sw_nii52007.pdf) that one can tell the processor that the memory should be accessed not using the cache by setting the MSB of the address to '1'. This application note is really interesting. In this document it's also mentioned that checksum generation could be greatly improved if using a dedicated hardware resources on the FPGA. Do you know if there is an IP core for the Triple-Speed Ethernet MegaCore core available?
