SOPC create 8bit ext tristate memory

i must use memory instead of register, because some external devices are memory (NVRAM f.e.). And we cannot have the gaps we get with register mode. In fact we need to have to lowest 4 external bytes must be the first 32bit data in nios memory, and the next 4 external byte the next 32bit data ...

I have used the avalon tristate slave.

All signals are of interface type "avalon_tristate_slave_0"

And the signal types are

data 8 bidir

write_n 1 input

read_n 1 input

irq_n 1 output

address 20 input

clk 1 input

chipselect_n input

The interface is set to memory(dynamic bus sizing) with 0 minimum arbitration shares.

The timing is as needed in nsec taken from the datasheets of the external devices.

So my concern is about memory dynamic bus sizing.

We had tried to implement this as we started with nios but failed.

I remember that we had to use register (nativ bis sizing) as this was the only chance that even with IORD_8DIRECT only a single byte access had been initiated.

My problem is that i have to design a tristate 8bit interface (like we use in those good old 8051 days) but the software must be able to use byte, halfword and word addressing mechanism and the 32, 16 or 8 bit access (read and write) must create 4, 2 or only 1 access to the external device depending on the nios access.

I hope that this tristate Bridge handles this correct.