Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThanks. Up to now I have been running with RO and RW data sections located in DTCM, with alt_load() copying disabled.
However for resilience in-service I need to be able to guarantee that the Nios SW can be re-booted without re-programming the FPGA. So I'm going to use the ITCM like a boot device, copying the RO and RW data sections to DTCM in the alt_load() phase, and protecting it from corruption. But (I think) I also need to connect the ITCM to the Nios data master in order to allow debugging via JTAG. The idea then is to protect ITCM from inadvertent writes unless debugging is specifically enabled via an externally programmed register. I'll try creating the conduit component.