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Altera_Forum
Honored Contributor
19 years agoSetup an IRQ on a component
Hi , I made a "counter" component which I want to interrupt NIOS when reaching 8'h7. I also created a control register in which is bit IRDY (Interrupt Ready) I have 2 questions fo...
Altera_Forum
Honored Contributor
19 years agoHello ,
I map the signals as following : module counter_avalon_interface ( clk , // global signal , clk , 1bit , input reset_n , // global signal , reset , 1bit , input chipselect , // avalon_slave 0 , chipselect , 1bit , input address , // avalon_slave_0 , address , 2bit , input write , // avalon_slave_0 , write , 1bit , input writedata , // avalon_slave_0 , writedata , 8bit , input read , // avalon_slave_0 , read , 1bit , input readdata , // avalon_slave_0 , writedata , 8bit , output counter_out, // avalon_slave_0 , writedata , 8bit , export intr // avalon_slave_0 , irq , 1bit ); and use this code in NIOS IDE to "process" the interrupt : # include <stdio.h># include <sys/alt_irq.h># include <io.h> # include "counter_routines.h"# include "system.h"# include "altera_avalon_uart_regs.h" void counter_isr( int context ); int main() { int context = 0; printf("Hello from Nios II!\n"); SetInterrupt( COUNTER_0_BASE ); // enable IRDY , my own HAL driver alt_irq_register( COUNTER_0_IRQ , &context , counter_isr ); while( 1 ) { } return 0; } void counter_isr( int context ) { // output 'Y' to UART IOWR_ALTERA_AVALON_UART_TXDATA( UART1_BASE , 'Y' ); } ------- It seemed that CPU wasn't interrupted. Anybody has got this issue before ? Thanks, Quan