Sending coefficients of degree 1000 from UART to custom logic with Nios II and SOPC.

I now know how to make a _hw.tcl file(with the sopc component generator) so I would have to generate a component with the signals to the RAM(adress out,wren out,ren out,data out,q in) and fsm(rdy out,done in) as conduit signals and signals to the component from the nios ii(coef in, coef out) as avalon-MM slaves . If this is correct I then would like to know how I can access these signals from the nios ii, do I have to write some kind of functions to access the slave registers? Or are there some automatic functions created that I can use to interface with the component(ie. to set the output wren to 1, something similar to the IOWR function)?

My second question is about the serializing the 2000 bits. Don't I have to enventually buffer them somewhere before the custom logic for the 62,5 clock signals and then feed them to my std_logic_vector(1999 downto 0) input? From your description I wasn't able to understand this. I understand that both the input and the output in the RAM is 32 bit wide, but how do I finally converge this to the custom logic input.

Thanks in advance,

Fred