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Ok so unfourtunatly I got a bit lost again.
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That is understandable, as you are new to this.
To implement your system, you need to understand several aspects of the tools. Rather than trying to understand them all at once, you need to take it step-by-step.
Step 1. Understand how Altera wants you to create systems. Go through this tutorial to understand this step.
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial Step 2. Learn how to use Modelsim to simulate a dual-ported RAM component (as created by the MegaFunction Wizard).
Your testbench would write coefficients to one side of the RAM, and assert a 'go' signal to your control FSM.
Your control FSM would wait for the 'go' signal, read the coefficients from the RAM, perform its processing, and then assert the 'done' signal.
Your testbench would wait for the 'done' signal, and then check the result - whatever that is - perhaps your control FSM can write the result(s) back to the dual ported RAM in another area.
Step 3. Learn how to create an Avalon-MM slave interface to a single-ported RAM, and how to describe this in an _hw.tcl file. From this experience, you will understand how to create an Avalon-MM slave interface to your component. We can come back to this once you have the other steps working. Its actually quite easy. However, I won't just 'give' you the code, you have to try and figure it out first (otherwise you won't really learn how it works).
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The plan is to instance the RAM in the SOPC builder or as a megafunction in quartus?
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You have to create a component that includes a RAM (which can be created using the MegaFunction Wizard), but then you also have to create a _hw.tcl file to describe your new component as a Qsys or SOPC builder component.
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if I understood correctly I would implement a Dual-port ram(from the altsyncram megafunction) and from the side of the A-port(from the SOPC system) I would have a 32 bit bus and from the B-port(FSM) I would have a 2000 bit bus.
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You already commented that your logic does not need all 2000-bits during the same clock cycle. If the RAM output is 32-bits, then you can read the 2000-bits in 2000/32 = 62.5 ~ 63 clocks.
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Since I'm new to this I also don't understand how to serialize the output from the SOPC,does the 2000 char table in the nios ii automatically serialize if there is only 32 bits output aviable, or do I have to manually divide the input 2000 char coefficients into 32 bit words diffrent with RAM adresses(so ~62,5 different adresses).
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Its your job to design the hardware. You need to use Modelsim to simulate the fundamental components offered by the FPGA, and then figure out how you can apply them to your system.
Following the steps above, you will get ideas on how to proceed.
Take small steps, and it'll be less intimidating.
Cheers,
Dave
Honored Contributor
