Honored Contributor
Honored ContributorSo the Avalon bus will be the bottleneck..Hmmm.
So what I really need to do is to run the bus at 100Mhz and NIOS at 50Mhz. If I can do this NIOS will only use 1/2 of the bandwidth and leave the rest to other devices. I think this is do-able, don't you? If a NIOS cpu only requests access for half the bus cycles the avalon bus should, in theory, give it half the access it wants. The same holds true for the current 1:1 condition. If 2 NIOSs run off a 50MHz bus at full speed, with no cache, then the access to the memory, for each, will average out to about 25MHz BW. For NIOS 1 this is easy to do because I have the source. I also have to tweak the other devices like the UARTs. If NIOS only asks for access every 2nd clock then it will only run like a 50MHz CPU with a 100MHz clock. For the 2nd master I probably need to do a 180 degree clock shift to ease out the bus, maybe not... I believe that this is going to become more important as time goes on. Ken, you commented the following:"i found that i could run out of onchip ram to 140mhz". If you could use DDR memory at 266MHz equivalent then it means that best case your system is only using 140MHz of it. DDR gives you the chance to run at 133 for 266 but still to execute 140MHz equi you need to run 140MHz. Memory will get faster DDR2- QDR etc... Somehow there must be an easy way for multiple NIOSs and other masters to run at full speed in parallel? Bottlenecks! The easy answer is put multiple sections of memory on the board, but many designers opt for the simplest design and or cheapest. If you sit with a design like mine that tops out at 75MHz(and with many boards in the field) and you have memory that SOPC can use at 100MHz, at least, then it means that there is room for improvement. So why the hell do I want to do what I want to do? Currently just shared VGA running off main memory. I also have another application. I am doing business with systems integration company. Their flagship product is designed and maintained by 5 entities, including themselves. They spend small fortunes on integration tools like custom networks and simulators. I proposed a NIOS system whereby there are 5 main NIOSs on one chip. The majority of the magic happens with memory blocks shared between the systems. So it makes sense that everything runs off one block of memory. They will physically save millions in R&D. Each company has its own serial download and debugging interface and I/O ports. Some of the apps only need small amounts of CPU power, like MMI. Others like the motor control needs DSP control loops and will probably require about 70% of the clock resources. This means that if I can run a StatixII at 200MHz I will at default have about 40MHz per CPU memory bandwidth. So here is what I propose: * SOPC is still spec-ed with a global frequency (so all the UART goodies runs from a stable source) * All other masters have a clock divider function (not just priority). (Thus any master like a NIOS, DMA or custom master). A NIOS can be programmed to run at full speed (undivided) or fractions. This means if 2 NIOSs are clock divided by 2 the example above they will run at 100MHz each. BUT you won't gain anything !!! Yet. But if you look at your memory you will notice that your DDRs can move 266Mega words per second. Thus with a divider of 2 you can run each to a max of 133MHz. Now add a small NIOS2e CPU for a stupid MMI controller with a LCD and key interface. On the current method this poor bugger will try to run at 1/3 the speed (shared between e.g. the two other NIOS2f CPUs). You probably only need a 10MHz CPU tops. So for this one you will divide its clock by 16. So although your main clock can be about 200MHz your NIOSIIe will only run at 12.5Mhz. Also using less power. This will several advantages: * Power * Loading * Keeping certain NIOS blocks close to a standard execution time . * Using faster memories -> More NIOSs per chip -> No degradation in performance. Victor
