Running SDRAM at double speed

Ken

My problem is that I am already sitting with current boards running at 60MHz. They actually top-out at 75 MHz. The reason why I don't go faster is power. The boards were designed with Nios1.2 in mind and then upgraded with NIOS1.3 with the old SDRAM controller. These boards ran at 40MHz. With a few tweaks I got the 60 MHz. I can go a bit faster but then my PSU, designed with the requirements at 40MHz, goes out of spec (1.5V side).

So I am stuck at 60MHz max. What I need is an onboard VGA controller. This will be a master sharing memory with my main NIOS master. To do 640x480 @ 60Hz the VGA controller will take up about 18 MHz bandwidth if everything goes its way. To reduce losing speed on my NIOS side I feel that I must keep the core at 60MHz, run the SDRAM at 100MHz and have about 20MHz BW spare. Looking at the documents it looks like the SDRAM must be in sync with the Avalon bus.

IF ... the Avalon bus can only start the transaction and wait for a busy signal to fall away it means the SDRAM controller can run at whatever speed it wants, doesn't it? My PC has a CPU speed of 2.5GHz, FSB of 400MHz and 400MHz memory. This holds true for two or more NIOS CPUs running at the same time. If you can run from cache it is cool, but if both masters move large blocks of memory then there is only one pipe running at X Hz. Thus 2 CPUs running at 50MHz from the same 50MHz SDRAM do not run as well as 2 from SDRAM clocked at 100MHz. I just feel it is a waste. Infact I am using PC133 spec.

Somehow some device must be able to wait for something?

Victor