Running Quartus 13.0sp1 Triple Speed Ethernet IP on uClinux

Hi Kazu,

Many thanks for your help. I have resolved the issue. The problem wasn't in the tx scatter gather DMA but the enet_gtx_clk along with timing constraint problem in the SDC. The Marvell 88E1111 gigabit ethernet transceiver requires the following interface signals

GTX_CLK -> PHY transmit clock (enet_gtx_clk)

TX_EN -> transmit control signal (enet_tx_en)

TXD[3:0] -> data transmit bus (enet_tx_d[3:0])

RX_CLK -> PHY receive clock (enet_rx_clk)

RX_DV -> receive control signal ( enet_rx_dv)

RXD[3:0] -> data receive bus (enet_rx_d[3:0])

The MAC must hold TX_EN (transmit control signal) low until the MAC has ensured the TX_EN is operating at the same speed as the PHY. However, because of the enet_gtx_clk isn't working properly, which it explain the TX_EN is always low I have mentioned from previous post. The key to my problem is I have a PLL generate frequency (125MHz, 25MHz, and 2.5MHz) to drive the MAC transmit clock and PHY GTX clock, which I though it was a correct thing to do since this is what it's in the board_portal_update example come with the board. However, the key to my solution is the PHY GTX clock require 90 degree phase shift from the MAC transmit clock. Therefore, the PLL should generate two sets of frequency, (125MHz, 25MHz, and 2.5MHz) to drive the MAC transmit clock and then another set with 90 degree phase shift (125MHz, 25MHz, and 2.5MHz) to drive the PHY GTX clock.

I am able to ping from both end but am trying to understand why I needed the 90deg phase shift for it enable to work properly. Does it makes any sense to you?

Yeung