Honored Contributor
Honored ContributorHello guys,
It's finally alive. And this is all thanks to you. First of all, the problem with compilation was caused by the enabled gpio drivers (as Antonie and Urmel suggested). Removing them from the kernel settings solved the problem. The problem with downloading the kernel to the DDR2 was caused by not following the guidance on (http://www.altera.com/support/kdb/solutions/rd07292010_420.html) carefully. I have 1 GB of DDR2, but changing the column and row address bit widths in the controller, I forced the sopc-generator to address it with 256MBs worth space. This way I kept the memory address in between 0x10000000-0x1FFFFFFF, as suggested. All the other modules need to be addressed between 0x0 and 0x0FFFFFFF. I have changed the DDR2_TOP_BASE to 0x10000000, and DDR2_TOP_SPAN to 268435456 (256Mb) in /nios2-linux/linux-2.6/arch/nios2/include/asm/nios.h, accordingly. In the make configuration, the "Link Address offset for booting" value is 0x02000000. I had the same error Antonie had with the timer. I fixed it thanks to Pierre. Now it is time to help Antonie =) If you want to debug the DDR2 against possible faults, you can use the program that comes with DE4 board. (DE4_Control_Panel). For a long time I blamed my own mistakes on the DDR, but it seems it works fine. You can try to write a big file to the DDR, and see if it writes correctly. For the DDR controller, I think you should make a fresh start with (\demonstrations\DE4_230\DE4_DDR2) project in DE4 cd, and make the changes one you are sure things work correctly. I would suggest you to delete the bridge (which connects the cpu to the ddr2 controller). I understand you don't need it for a simple design; the necessary circuit will be implemented on LUTs. (http://www.alteraforum.com/forum/showthread.php?t=29562). I hope this is helpful. Please contact me anytime you want. Cheers, Turhan
