problem with LCD Refreshing rate

1) Instead of 3 writes, do one - using the data and address lines.

2) Put clock domain crossing logic between the Avalon slave and your SRAM+LCD logic (or run everything off exactly the same clock).

If the SOPC builder has added a clock crossing bridge it will significantly increase the cycle time and slow down your transfer rates.

Since the Avalon 'bus' is slave arbited, you could almost certainly have used the standard SRAM interface and given the LCD memory reads higher priority than the nios accesses. Then your LCD driver/dma would need to do Avalon master transfers to SRAM (would these need to be burst transfers??), maybe a standard DMA block could be used - dunno.

You might need to look at the generated code for your copy loop (etc), my suspicions are that the compiler will generate better code if your C has a pointer to the Avalon slave register area - rather than using the ALT_IOWR() (and similar) defines.

I arranged for the 'global pointer' to cover both internal (tightly coupled) memory and IO, and used the linker to assign the io addresses (to give the C variables fixed addresses). This gave single-cycle accesses to them.

This does require a compiler patch to allow global pointer accesses to structures (see wiki), and wont work if you are using the data cache.