power failure interrupt on NIOS 2

Rick,

Short answer: if you use the built-in interrupt support, then ues, irq0 is higher priority than irq5.

Longer answer: The hardware no longer cares -- interrupt behavior is entirely under software control. I don't have the code in front of me, but I think the way the default Nios II ISR handler works is to loop through pending interrupts, lowest ISR number first. During this time, lower priority interrupts are disabled using a CPU register.... the upside to this is that you can change this code if you're adventurous to meet exact system needs.