Ping-Pong Buffer with SGDMA

It's been a while since I have used that DMA after looking at the documenation it appears that there is a bit in the control register (not the descriptor) that you can set to have the DMA interrupt after every descriptor is completed. So in your ISR you would have to keep track of which descriptor completed.

In your linked list you would have to make sure the DMA doesn't move to the next descriptor automatically otherwise whatever else in your system is working on the buffer might not be done with it yet. So I'm assuming you don't set the owned by hardware bit at the end of your linked list and wait for the DMA to complete first right? (otherwise I think you have a bigger syncornization problem to think about).

Have you seen my DMA yet? It might be a lot easier to use for what you are trying to do: http://www.alterawiki.com/wiki/modular_sgdma I'm debugging an issue in it where if one packet starts the clock cycle after the previous one completed then the first address is not written to, but other than that it works pretty good.