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OK, my design has a NIOS II based SOC and a PCIe Altera IP in the top-level. The NIOS II and all peripherals run on 100Mhz but interface via MM-FIFOs at 50Mhz to the PCIe IP. I have a simple utility programs that sends config. packets to the PCIe IP and it replies correctly with device ID, etc. The card is plugged in a system slot on the bus AND it provides the PCIe clock to the bus. I took over the design from someone else... so I am not sure really what differentiate a RootPort from an EndPoint other than who provides the 100Mhz clock. I did not know that an EndPoint can do enumeration.
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You took over the design from someone else, so first you need to understand it.
If you can answer my questions, then you'll be a little further along in understanding the design you have inherited.
Can you post a link to the motherboard or backplane that you are plugging the board into.
As I commented above, the Stratix IV Development Board is a PCIe peripheral board, so it only makes sense that it gets configured as a PCIe end-point. When your test system powers on, the root-complex (typically a PC) writes to configuration space to tell each of the PCIe-to-PCIe bridges what their address ranges are, and writes to PCIe peripherals to tell them what their PCIe addresses are. If your root-complex (host) was running Linux, you could type lspci and see the addresses that the BIOS assigned to the PCIe bridges and peripheral boards.
You comment that
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I have a simple utility programs that sends config. packets to the PCIe IP and it replies correctly with device ID, etc.
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Where is this program running? On a NIOS II processor inside an FPGA on the Stratix IV kit, or on the host PC?
Cheers,
Dave
Honored Contributor
