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The 100Mhz is only on the NIOS II Avalon bus, the PCIe Avalon-MM- FIFOs have 100Mhz on one side and 50Mhz on the PCIe side.
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You state that you've created a PCIe "root complex" device. However, I believe this only makes sense if you are in the "system" slot of the bus. If you are in a peripheral slot, you would configure the PCIe as an "end-point". An end-point can still enumerate the PCIe bus, but it has a 100MHz input clock as a reference.
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I can send config. packets to the PCIe IP and it responds correctly.
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Sending from what? Your NIOS processing inside the FPGA, or another peripheral in your motherboard?
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Can you tell me more about "building UBoot for NIOS II" ? (I am a HW guy...) We don't intend to use Linux for now.
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Sorry, I haven't used it. Create a new thread with a new title and someone else can probably help.
Cheers,
Dave
Honored Contributor
