non-cacheable instruction memory

I solved the problem using the section .ddr_sdram_0 (name of section corresponding to my on-chip memory) to load the cacheable part of the code.

The instruction is:

.section .ddr_sdram_0

inserted before the part of code to load on that memory.

Now observing the content of my .elf file the instructions corresponding to cacheable and not cacheable parts of my code are loaded at correct addresses.

But when I debug the code on my board, when the code jumps to cacheable part there aren't the same instructions listed in .elf file.

At the same address the .elf file contains a different instruction compared to the disassembly of the debugging code.

What does it means?:confused::confused::confused::confused:

Thank you.

Rolfo Daniele