non-cacheable instruction memory

That's correct, if you want some of your code to be cacheable and the rest be uncacheable using the instruction master for cacheable accesses (need a Nios 's' or 'f' core) and the tightly coupled instruction master for the uncacheable accesses is what you'll need to do.

Determining where code winds up in memory is done by the linker. Both your main memory and on-chip tightly coupled memories should each show up in BSP editor along with their linker section names. There is a gcc attribute called "section" which you can use in your code to inform the linker what section your code should be placed in. If you take a look at the tightly coupled memory design example on altera.com you'll see an example of this for some C code. I would imagine there is a way to do this with assembly code as well.... not sure though since I typically write assembly at a function level which I could just use the C prototype to do this type of linking.

There might be easier ways, if you explained more about what you are trying to do maybe we can make a better suggestion.