NiosII University IP Core VGA

Please Help!

Using Altera DE1 board.

Added the University IP VGA core downloadable from Alteras Website to my SOPC builder. Have been simulating in Quartus II and cannot get any signals for V_sync and H_sync. There is a 25Mhz clock to the VGA Core, and 50Mhz clock to the slaves as specified in the provided PDF.

Question: Is there something I am missing? Is there a initialization, or a start bit to trigger the VGA core to start the timing? The H and V sync signals start low, but once the vga clock begins they go high and stay high. Since they are active low, thats whats expected without a clock, but there is a clock.

All suggestions would be helpful.