Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNiosII SPI Core problem
Hi, all i use a SPI core in my nios system. when i used the function "alt_avalon_spi_command()" to sent a "who am i" command to the peripheral, it received no data. so i use signalTap to debu...
Altera_ForumHonored Contributor
Honored ContributorHi everyone!
I'm also using an SPI core to connect my peripheral to nios and I also send "who_am_i" command, but I'm experiencing some difficulties. When I send data using altera_avalon_spi_command(), here are the signals from SignalTap Logic Analyzer (SCLK, SS_n, MOSI, MISO): https://www.alteraforum.com/forum/attachment.php?attachmentid=5300 My SPI is configured as master, SCLK=10MHz, Data Register width = 8, Clock polarity = 1, Clock phase = 1. I can see that in q3ccn's picture spi clock exists as long as SS_n signal is deasserted which doesn't happen in my case. So, I suppose that in the first clock cycle in my picture, the data (0x8F) is sent over MOSI line, but what happens in the other cycle? Why is there such a big period between these cycles? Is it possible that data is sent again in that second cycle or the received data is sampled from the MISO line? When I configure MISO pin as an input pin in quartus, should I enable pull-up resistor or it is not necessary? Thanks for any help.
