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Altera_Forum
Honored Contributor
14 years agoI have never really used signal tap since my motive here is to quickly get a NIOSII system up and running so I can play around with Linux/uCLinux, but it looks like I'd have to delve a little deeper into EDA stuff than I had initially expected :rolleyes: . So Ill look into that.
By the way, when you say connect the PLL out clk to the LED, it is in the schematic right? I mean just connect it directly to one of the LEDs so I can watch it go 'blinky'?? :o. But me as a human won't be able to distinguish between a steady LED and an oscillating one as 85MHz is to too much to keep track of using my human eye. May be I've got you wrong here. Could you please elaborate? Additionally I am using the-create_base_clocks switch while using the derive_pll_clocks timequest command so (as per the cookbook) the source clock setting is already calculated by timequest. You can take a look at the SDC file I am attaching with post. I am also attaching the timing failure reports along with this post. The 'Slow model' and the 'multi-corner timing analysis' failed. Hope these reports along with the SDC file will give us a clue..the sdc file has been appended the .txt extension. Keen to hear from you, Regards, Aijaz