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Altera_Forum
Honored Contributor
14 years agoFor a correct timing analysis, you should create a sdc file that describes all your clock sources. Timequest should get your timing requirements from that and will tell you if your design fullfills them. This should be the first thing you do.
Are you using a pll? If yes have a look at its "locked" output, to verify that it is getting a correct clock signal. Also be careful with the reset signal. The reset input on a SOPC design is active low, so must be high when you try to communicate with the Nios processor.