NIOS SDRAM performance

Hi Dirk,

I was trying to think why I didn't suspect the SDRAM/SDRAM controller and I remembered why.

When I went to a NiosI class the instructor said the new SDRAM controller provided one-clock per word performance. I asked him why then cache was important. (one clock is one clock right ?) He said that was a good question and took my name and# to get back with me. (still no call)

I also found the shiny brochure for one of my 3 devkit boards and it says this:

"Enhanced SDRAM Controller"

"The NIOS SDRAM controller has been enhanced to support pipelined data transactions; it provides single-cycle access to low cost single data rate (SDR) SDRAM devices"

I'm not as hardware centric as I would like to be, but these two statements tell me not to expect 12 cycle access. Perhaps it's a matter of semantics and the fault is my misunderstanding of the exact meaning of the terms?

Still the bottom line is how do we get decent SDRAM performance? New version of SDRAM controller? Secret .ptf settings? 3rd party controller?

Any ideas?

Thanks,

Ken