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Altera_Forum
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21 years ago

NIOS SDRAM performance

I have measured the speed of memcpy's of NIOS2. I use optimized code consisting of four consecutive READs and four consecutive write accesses. Code snippet: while (i--) { d0 = __built...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Dirk,

Thanks for the good info. I was planning on writing the exact code you did for moving/copying SDRAM and I just assumed it would have good performance due to back to back reads.

Looking at the datasheet a read should take the number of clocks you have set for CAS latency in most situations. (certainly back to back reads on the same row) I count about 12 clocks in your trace!

Since SDRAM is so popular for NIOS/SOPC systems this would be an excellent place to focus efforts to increase performance.

It would be nice if someone from Altera could at least comment on this topic.

If Altera has no plans to improve this I would be willing to fund the improvements if anyone knows how to modify/replace the SDRAM controller. (assuming its legal to modify the SDRAM controller)

Anyone know of a better SDRAM controller that is SOPC builder ready?

Ken