Altera_Forum
Honored Contributor
14 years agoNios program runs slower when loaded from EPCS flash
Hi,
I have written some Nios software that requires real-time operation. i.e. It must execute fast enough to run indefinitely without bottlenecks. When I run the program from the Nios Eclipse IDE everything works until I power down. To make my firmware and software persistent, I want the SOF firmware and ELF software to load from my EPCS flash and run automatically. So, I've changed the CPU Reset Vector in Qsys to point to my EPCS flash controller instead of SDRAM. I generated the Qsys files, synthesized the Verilog files in Quartus, generated my Nios BSP, rebuilt the application, and used the Nios II Flash Programmer GUI to program the EPCS. At power on, everything appears to be working. The FPGA is configured and my software runs as expected. The problem is that my program now reaches a bottleneck after 4 seconds and halts. My computations are lagging behind from the start and eventually fails. If I haven't changed anything besides the CPU's reset vector, what could have changed my code's operation? I've run the same software with the performance counter and both cases appear identical! -J